1. Field of the Invention
The present invention relates to an oscillation circuit for outputting an oscillation waveform from an output terminal of an amplifier after feedback-controlling a solid-state oscillator using the amplifier, more particularly to a technology for protecting the circuit from the ESD (electrostatic discharge), more specifically, for protecting the circuit from a surge voltage resulting from the electrostatic discharge.
2. Description of the Related Art
FIG. 5 shows a circuit configuration of an oscillation circuit including an amplifier and a solid-state oscillator according to the conventional technology. A solid-state oscillator X formed from a ceramic oscillator, a crystalline oscillator or the like is connected to between a bonding pad T1 and a boding pad T2. The solid-state oscillator X is provided outside of the LSI. Between connecting points of the solid-state oscillator X on both sides thereof and a low-voltage-side power supply VSS (GND) are respectively provided oscillation capacitance elements C1 and C2. Inside the LSI, an input terminal of an amplifier A is connected to the bonding pad T1, and an output terminal of the amplifier A is connected to the bonding pad T2. A bias feedback resistor Rf is connected to both ends of the amplifier A. In the drawing, a typical example of the amplifier A, which is an inverter (inversion amplifier), is shown. An oscillation output terminal OUT is connected to the output terminal of the amplifier A via a waveform shaping circuit 1. An input-side ESD protecting circuit B1′ is inserted between the input terminal of the amplifier A and the bonding pad T1, and an output-side ESD protecting circuit B2 is inserted between the output terminal of the amplifier A and the boding pad T2. The input-side ESD protecting circuit B1′ comprises a power-supply-side ESD protecting element G1 and a ground-side ESD protecting element G2. The output-side ESD protecting circuit B2 comprises a power-supply-side ESD protecting element E1 and a ground-side ESD protecting element E2.
A P-channel-type MOS transistor constitutes each of the power-supply-side ESD protecting elements G1 and E1 provided on the upper side in the drawing. Gates of the power-supply-side ESD protecting elements (transistors) G1 and E1 are connected to sources and a power-supply wire via resistors. Drains of the power-supply-side ESD protecting elements (transistors) G1 and E1 on one side are connected to a node N1 which is the input terminal of the amplifier A, and drains of the power-supply-side ESD protecting elements G1 and E1 on the other side are connected to a node N2 which is the output terminal of the amplifier A.
An N-channel-type MOS transistor constitutes each of the ground-side ESD protecting elements G2 and E2 provided on the lower side in the drawing. Gates of the ground-side ESD protecting elements G2 and E2 are connected to sources and a ground wire via resistors. Drains of the ground-side ESD protecting elements (transistors) G2 and E2 on one side are connected to the node N1 which is the input terminal of the amplifier A, and drains of the ground-side ESD protecting elements G2 and E2 on the other side are connected to the node N2 which is the output terminal of the amplifier A.
In the oscillation circuit thus constituted, the solid-state oscillator X is connected to the bonding pad T1 and the bonding pad T2 to generate the oscillation, and a waveform of the oscillation is inputted to the amplifier A. The bias feedback resistor Rf is operated in an active region by the inverter (amplifier A) used as the inversion amplifier, and the positive feedback control is thereby executed to the solid-state oscillator X via the amplifier A. The oscillation capacitance elements C1 and C2 invert a phase of an oscillation signal in cooperation with the solid-state oscillator X (particularly, its inductive property).
In the described manner, an amplitude of the oscillation is gradually increased, and the oscillation is then continued in a state where the amplitude is stabilized after a certain period of time. The stabilized oscillation waveform is shaped by the waveform shaping circuit 1, and then outputted from the oscillation output terminal OUT and supplied to the LSI. In the normal operation, the power-supply-side ESD protecting element G1 and the ground-side ESD protecting element G2 are in the non-conductive state, and the power-supply-side ESD protecting element E1 and the ground-side ESD protecting element E2 are also in the non-conductive state.
When the surge voltage resulting from the electrostatic discharge is applied to the bonding pad T1 from outside, the ESD protecting circuit B1′ on the input side is operated. More specifically, when the positive surge voltage is applied, the avalanche breakdown makes the power-supply-side ESD protecting element G1 conducted, and the generated charges are thereby speedily let out to the power-supply wire VDD. When the negative surge voltage is applied, the avalanche breakdown makes the ground-side ESD protecting element G2 conducted, and the generated charges are thereby speedily let out to the ground wire VSS.
When the surge voltage resulting from the electrostatic discharge is applied to the bonding pad T2 from outside, the ESD protecting circuit B2 on the output side is operated. More specifically, when the positive surge voltage is applied, the avalanche breakdown makes the power-supply-side ESD protecting element E1 conducted, and the generated charges are thereby speedily let out to the power-supply wire VDD. When the negative surge voltage is applied, the avalanche breakdown makes the ground-side ESD protecting element E2 conducted, and the generated charges are thereby speedily let out to the ground wire VSS.
FIG. 6 shows a circuit configuration of another oscillation circuit including an amplifier and a solid-state oscillator according to the conventional technology. In FIG. 6, the same reference symbols as those shown in FIG. 5 denote the same components. The configuration shown in FIG. 6 is characterized in that a diode is a main circuit element in each of an input-side ESD protecting circuit B1 and an output-side ESD protecting circuit B3. The input-side ESD protecting circuit B1 comprises a power-supply-side ESD protecting element 2d and a ground-side ESD protecting element 2s. The output-side ESD protecting circuit B3 comprises a power-supply-side ESD protecting element 6d and a ground-side ESD protecting element 6s. A diode D1 constitutes the powers-supply side ESD protecting element 2d, and a diode D5 constitutes the power-supply-side ESD protecting element 6d. A diode D2 constitutes the ground-side ESD protecting element 2s, and a diode D6 constitutes the ground-side ESD protecting element 6s. 
In the power-supply-side ESD protecting element 2d (diode D1) provided on the upper side in the drawing, an N-type diffusion layer is connected to the power-supply wire VDD, and a P-type diffusion layer is connected to a node N1 on the input side of the amplifier A. In the ground-side ESD protecting element 2s (diode D2) provided on the lower side in the drawing, a P-type diffusion layer is connected to the ground wire VSS, and an N-type diffusion layer is connected to the node N1. In the power-supply-side ESD protecting element 6d (diode D5) provided on the upper side in the drawing, an N-type diffusion layer is connected to the power-supply wire VDD, and a P-type diffusion layer is connected to a node N2 on the output side of the amplifier A. In the ground-side ESD protecting element 6s (diode D6) provided on the lower side in the drawing, a P-type diffusion layer is connected to the ground wire VSS, and an N-type diffusion layer is connected to the node N2.
In the oscillation circuit shown in FIG. 6, the oscillation waveform is outputted from the oscillation output terminal OUT and supplied to the LSI in a manner similar to the oscillation circuit shown in FIG. 5. In the normal operation, the power-supply-side ESD protecting element D1 and the ground-side ESD protecting element D2 are in the non-conductive state, and the power-supply-side ESD protecting element D5 and the ground-side ESD protecting element D6 are also in the non-conductive state.
When the surge voltage resulting from the electrostatic discharge is applied to the bonding pad T1 from outside, the ESD protecting circuit B1 on the input side is operated. When the surge voltage resulting from the electrostatic discharge is applied to the bonding pad T2 from outside, the ESD protecting circuit B3 on the output side is operated. As a result, the charges generated from the application of the surge voltage are thereby speedily let out to the ground wire VSS or the power-supply wire VDD.
In the oscillation circuits shown in FIG. 5, a parasitic capacitance generated inside may prevent the output of the oscillation waveform from the oscillation output terminal OUT. More specifically, when the oscillation circuit is being oscillated, a potential of the gate of the MOS transistor is increased by the parasitic capacitance (coupling capacitance Cp) generated between the gate of the N-channel MOS transistor in the ground-side ESD protecting element G2 and the node N1, and a potential between the relevant gate and source becomes at least a threshold voltage of the MOS transistor. As a result, the MOS transistor is conducted without the application of the surge voltage, which generates the flow of an ON current I1 to the ground wire VSS. The flow of the current I1 thus generated is drawn to the ground-wire side, and the amplitude of the oscillation waveform, which is originally supposed to be 3.3 V, thereby becomes lower than 3.3 V.
FIG. 7 shows the states of the oscillation waveforms at the node N1, node N2 and oscillation output terminal OUT. Under the influence of the current I1, the amplitude of the oscillation waveform at the node N1 is between a voltage smaller than 3.3 V (for example, 2.0 V) and 0 V. The amplitude of the oscillation waveform at the node N2 is between a voltage larger than 0 V (for example, 3.3−2.0=1.3 V) and 3.3 V because the oscillation waveform at the node N1 is inverted by the amplifier A (inverter). However, the oscillation circuit is subject to such a condition that the oscillation waveform at the node N2 (for example, 1.3 V-3.3 V) cannot exceed a threshold voltage on the L-level side of the waveform shaping circuit 1 (inverter). Therefore, the oscillation waveform is not outputted to the oscillation output terminal OUT, and the voltage outputted from the relevant terminal constantly has the waveform of 0 V. In other words, the oscillation waveform cannot be outputted from the oscillation output terminal OUT due to the parasitic coupling capacitance Cp.
In the oscillation circuit shown in FIG. 6, when the surge voltage resulting from the electrostatic discharge is applied to the bonding pad from outside, the amplifier A may be broken down because the MOS transistor constitutes the amplifier A. Below is described a reason for the possible breakdown. If the ESD protecting circuit B3 shown in FIG. 6 is configured in a manner similar to the ESD protecting circuit shown in FIG. 5 (MOS transistor is its main circuit element), breakdown voltages of the MOS transistor of the amplifier A and the ESD protecting circuit B3 are equal to each other, which prevents the breakdown of the amplifier A caused by the surge voltage. However, in the ESD protecting circuit B3 shown in FIG. 6, in which the diode is its main circuit element, the breakdown voltage of the MOS transistor of the amplifier A is lower than the breakdown voltage of the ESD protecting circuit B3. Accordingly, the amplifier A may be broken down when the surge voltage resulting from the electrostatic discharge is applied to the bonding pad from outside.